Post by account_disabled on Nov 23, 2017 3:20:38 GMT -5
Hi,
We would like to store the input signal (raw data from adc0) in the new free RAM memory and then compare it with a newly acquired signal from adc0. The goal of our application is a pattern detection.
To check if we have a pattern in memory we want to playback the pattern in loop on the pcie (velocia packet) of adc1 (during that time there is no acquisition on adc1) and visualize it on snap.
How can we reduce the vfifo data buffer size to use the rest for our application?
Please help.
Thanks!
I didn't find the right solution from the Internet.
References www.innovative-dsp.com/forum/viewtopic.php?t=3124
Corporate Explainer Video
We would like to store the input signal (raw data from adc0) in the new free RAM memory and then compare it with a newly acquired signal from adc0. The goal of our application is a pattern detection.
To check if we have a pattern in memory we want to playback the pattern in loop on the pcie (velocia packet) of adc1 (during that time there is no acquisition on adc1) and visualize it on snap.
How can we reduce the vfifo data buffer size to use the rest for our application?
Please help.
Thanks!
I didn't find the right solution from the Internet.
References www.innovative-dsp.com/forum/viewtopic.php?t=3124
Corporate Explainer Video